SH7058 Datasheet, PDF (629/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
2
TSR2
0
R
Timer Compare Match Flag 1
Indicates that a compare-match condition
occurred to the timer compare match register 1
(TCMR1). When the value set in TCMR1 matches
the timer value (TCMR1 = TCNTR), this bit is set.
This bit is not set if the TCMR1 value is H'0000.
Also, this bit is read-only and is cleared when
IRR15 (timer compare match interrupt 1) is
cleared.
0: Timer compare match has not occurred to
TCMR1
Clearing condition: Writing 1 to IRR15 (timer
compare match interrupt 1)
1: Timer compare match has occurred to TCMR1
Setting condition: TCMR1 matches the timer
value (TCMR1 = TCNTR)
1
TSR1
0
R
Timer Compare Match Flag 0
Indicates that a compare-match condition
occurred to the timer compare match register 0
(TCMR0). When the value set in TCMR0 matches
the timer value (TCMR0 = TCNTR), this bit is set.
This bit is not set if the TCMR0 value is H'0000.
Also, this bit is read-only and is cleared when
IRR14 (timer compare match interrupt 0) is
cleared.
0: Timer compare match has not occurred to
TCMR0
Clearing condition: Writing 1 to IRR14 (timer
compare match interrupt 0)
1: Timer compare match has occurred to TCMR0
Setting condition: TCMR0 matches the timer
value (TCMR0 = TCNTR)
0
TSR0
0
R
Timer Overrun Flag
Indicates that the timer has overrun and is reset to
H'0000. This bit is set even when TCMR0 is set to
H'FFFF and is enabled to clear the timer value.
0: Timer has not overrun
Clearing condition: Writing 1 to IRR13 (timer
overrun interrupt)
1: Timer has overrun
Setting condition: When the timer value
changes the value from H'FFFF to H'0000
Rev. 3.0, 09/04, page 588 of 1086