SH7058 Datasheet, PDF (610/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.5.2 Transmit Cancel Register n (TXCR1n, TXCR0n) (n = 0, 1)
TXCR1 and TXCR0 are 16-bit readable/conditionally-writable registers. TXCR1 controls mailbox
31 to mailbox 16, and TXCR0 controls mailbox 15 to mailbox 1. This register is used by the host
CPU to request the transmission wait messages in TXPR to be cancelled. To clear the
corresponding bit in TXPR, the host CPU must write 1 to the bit in TXCR. Writing 0 is ignored.
When transmission cancellation has succeeded, the CAN controller clears the corresponding
TXPR and TXCR bits, and sets the corresponding ABACK bit. However, once a mailbox has
started a transmission, it cannot be cancelled by this bit. In such a case, if the transmission finishes
in success, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the
corresponding TXACK bit, however, if the transmission fails due to a bus arbitration loss or an
error on the bus, the CAN controller clears the corresponding TXPR and TXCR bits, and sets the
corresponding ABACK bit. If an attempt is made by the host CPU to cancel a mailbox
transmission that is not transmit-waiting, it shall have no effect, and will be automatically cleared
when an internal arbitration for transmission runs.
Important: For details on the method of canceling a transmit wait, see section 16.7, Operation.
Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see
section 16.8, Usage Notes.
• TXCR1n (n = 0, 1)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCR1[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name
Initial Value R/W Description
15 to 0 TXCR1[15:0] 0
R/W*
Request the corresponding mailbox, that is in
the queue for transmission, to cancel its
transmission wait. Bits 15 to 0 correspond to
mailboxes 31 to 16 and TXPR1[15:0]
respectively.
0: Corresponding mailbox is in transmit
message cancellation idle state
Clearing condition: Completion of transmit
wait cancellation (automatically cleared)
1: Transmit wait cancellation request made for
corresponding mailbox
Note: * 1 can be written only to a mailbox that is requested for transmission or set for
transmission.
Rev. 3.0, 09/04, page 569 of 1086