SH7058 Datasheet, PDF (159/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

7.3.3 IRQ Status Register (ISR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
IRQ0F
Initial value: 0
R/W: R/W
6
IRQ1F
0
R/W
5
IRQ2F
0
R/W
4
IRQ3F
0
R/W
3
IRQ4F
0
R/W
2
IRQ5F
0
R/W
1
IRQ6F
0
R/W
0
IRQ7F
0
R/W
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0–IRQ7. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing 0 to IRQnF after reading IRQnF = 1.
A reset and hardware standby mode initialize ISR but software standby mode does not.
• Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
• Bits 7 to 0—IRQ0–IRQ7 Flags (IRQ0F–IRQ7F): These bits display the IRQ0–IRQ7 interrupt
request status.
Bits 7-0:
IRQ0F–IRQ7F Detection Setting
0
Level detection
Edge detection
Description
No IRQn interrupt request exists
[Clearing condition]
When IRQn input is high
No IRQn interrupt request was detected
(Initial value)
[Clearing conditions]
• When 0 is written after reading IRQnF = 1
• When IRQn interrupt exception processing has been
executed
1
Level detection
Edge detection
n = 7 to 0
An IRQn interrupt request exists
Setting condition: When IRQn input is low
An IRQn interrupt request was detected
Setting condition: When a falling edge occurs at an IRQn
input
Rev. 3.0, 09/04, page 118 of 1086