SH7058 Datasheet, PDF (352/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 0—Interval Interrupt Bit 10 (ITVE10): INTC interval interrupt setting bit corresponding to
bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVE10x, the result is stored in
IIF2x in TSR0, and an interrupt request is sent to the CPU.
Bit 0: ITVE10x
0
1
x = A or B
Description
Interrupt request (ITV2x) by rise of TCNT0 bit 10 is disabled
Interrupt request (ITV2x) by rise of TCNT0 bit 10 is enabled
(Initial value)
For details, see section 11.3.7, Interval Timer Operation.
11.2.8 Trigger Mode Register (TRGMDR)
The trigger mode register (TRGMDR) is an 8-bit register. The ATU-II has one TRGMDR register.
Bit: 7
6
5
4
3
2
1
0
TRGMD —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
TRGMDR is an 8-bit readable/writable register that selects whether a channel 1 compare-match is
used as a channel 8 one-shot pulse start trigger or as a one-shot pulse terminate trigger when
channel 1 and channel 8 are used in combination.
TRGMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—Trigger Mode Selection Register (TRGMD): Selects the channel 8 one-shot pulse start
trigger/one-shot pulse terminate trigger setting.
Bit 7: TRGMD
0
1
Description
One-shot pulse start trigger (TCNT1B = OCR1)
One-shot pulse terminate trigger (TCNT1A = GR1A–GR1H)
One-shot pulse start trigger (TCNT1A = GR1A–GR1H)
One-shot pulse terminate trigger (TCNT1B = OCR1)
(Initial value)
• Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 3.0, 09/04, page 311 of 1086