SH7058 Datasheet, PDF (586/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
5
MCR5
0
R/W HCAN-II Sleep Mode
Enables or disables sleep mode transition. When
this bit is set, sleep mode is enabled. The HCAN
waits for the completion of the current bus access
before entering sleep mode. Until this mode is
terminated the HCAN will ignore CAN bus
operation. The two error counters (REC, TEC) will
retain the same value during and after sleep
mode. This mode will be exited in two ways:
• Write 0 to this bit
• If MCR7 is enabled, after detecting a dominant
bit on the CAN bus
When exiting this mode, the HCAN will
synchronize with the CAN bus (by checking for 11
recessive bits) before restart. This means that,
when the second way is used, the HCAN cannot
receive the first message, however, CAN
transceivers have the same feature, and software
needs to be designed in this manner.
Note: This mode is same as setting the module to
halt mode and stopping the clock. This
means that, the interrupt is generated from
IRR0 when entering sleep mode. During
sleep mode, only the MPI block is
accessible, i.e., MCR/GSR/IRR/IMR are
accessible. However, IRR1 cannot be
cleared during sleep mode as it is an ORed
signal of RXPR that cannot be cleared
during sleep mode, therefore, it is
recommended to set halt mode first and
then make a transition to sleep mode.
0: HCAN sleep mode is exited
1: Transition to HCAN sleep mode enabled
Important: Usage of sleep mode is limited. Be
sure to carefully read section 16.8, Usage Notes.
Rev. 3.0, 09/04, page 545 of 1086