SH7058 Datasheet, PDF (223/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Legend:
SCI0, SCI1, SCI2, SCI3, SCI4:
Serial communication interface channels 0–4
A/D0, A/D1, A/D2:
A/D converter channels 0–2
HCAN0:
Controller area network-II channel 0
ATU-II:
Advanced timer unit
TDR0, TDR1, TDR2, TDR3, TDR4: SCI0–SCI4 transmit data registers
RDR0, RDR1, RDR2, RDR3, RDR4: SCI0–SCI4 receive data registers
ADDR0–ADDR11:
A/D0 data registers
ADDR12–ADDR23:
A/D1 data registers
ADDR24–ADDR31:
A/D2 data registers
MB0–MB15:
HCAN0 message data
Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral
module (excluding DMAC, BSC, and UBC)
10.3.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a
channel according to the following priority order:
• CH0 > CH1 > CH2 > CH3
10.3.4 DMA Transfer Types
The DMAC supports the transfers shown in table 10.3. It operates in dual address mode, in which
both the transfer source and destination addresses are output. The dual address mode consists of a
direct address mode, in which the output address value is the object of a direct data transfer, and
an indirect address mode, in which the output address value is not the object of the data transfer,
but the value stored at the output address becomes the transfer object address. The actual transfer
operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and
burst mode.
Table 10.3 Supported DMA Transfers
Transfer Source
External memory
Memory-mapped
external device
On-chip memory
On-chip peripheral
module
External
Memory
Supported
Supported
Supported
Supported
Transfer Destination
Memory-Mapped On-Chip
External Device Memory
Supported
Supported
Supported
Supported
Supported
Supported
Supported
Supported
On-Chip
Peripheral Module
Supported
Supported
Supported
Supported
Rev. 3.0, 09/04, page 182 of 1086