SH7058 Datasheet, PDF (1118/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table A.2 Register States in Reset and Power-Down States (cont)
Reset State Power-Down State
Type
Name
Hardware Software
Power-On Standby Standby
Power-down
state related
SBYCR
SYSCR1, SYSCR2
Initialized Initialized Held
MSTCR
Controller
area network
MCR
GSR
Initialized Initialized Initialized
(HCAN)
HCAN_BCR 0/1
IRP
IMR
TXPR 0/1
TXCR 0/1
TXACK 0/1
ABACK 0/1
RXPR 0/1
RFPR 0/1
MBIMR 0/1
UMSR 0/1
TCNTR
TCR
TSR
TMR
TDCR
LOSR
CCR
CMAX
ICR 0/1
TCMR 0-2
MB
Undefined Held
Held
High-performance SDIR
user debug
SDSR
interface (H-UDI)
SDDRH, SDDRL
Held
Held
Held
Note: * Bit 7 (FLER) is held, and bit 0 (SCO) is initialized.
Sleep
Held
Held
Held
Held
Rev. 3.0, 09/04, page 1077 of 1086