SH7058 Datasheet, PDF (347/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 8—Overflow Interrupt Enable 11 (OVE11): Enables or disables interrupt requests by
OVF11 in TSR11 when OVF11 is set to 1.
Bit 8: OVE11
0
1
Description
OVI11 interrupt requested by OVF11 is disabled
OVI11 interrupt requested by OVF11 is enabled
(Initial value)
• Bits 7 to 2—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 1—Input Capture/Compare-Match Interrupt Enable 11B (IME11B): Enables or disables
interrupt requests by IMF11B in TSR11 when IMF11B is set to 1.
Bit 1: IME11B
0
1
Description
IMI11B interrupt requested by IMF11B is disabled
IMI11B interrupt requested by IMF11B is enabled
(Initial value)
• Bit 0—Input Capture/Compare-Match Interrupt Enable 11A (IME11A): Enables or disables
interrupt requests by IMF11A in TSR11 when IMF11A is set to 1.
Bit 0: IME11A
0
1
Description
IMI11A interrupt requested by IMF11A is disabled
IMI11A interrupt requested by IMF11A is enabled
(Initial value)
11.2.7 Interval Interrupt Request Registers (ITVRR)
The interval interrupt request registers (ITVRR) are 8-bit registers. The ATU-II has three ITVRR
registers in channel 0.
Channel
0
Abbreviation
ITVRR1
ITVRR2A
ITVRR2B
Function
TCNT0 bit 6 to 9 interval interrupt generation and A/D2 converter
activation
TCNT0 bit 10 to 13 interval interrupt generation and A/D0
converter activation
TCNT0 bit 10 to 13 interval interrupt generation and A/D1
converter activation
Rev. 3.0, 09/04, page 306 of 1086