SH7058 Datasheet, PDF (537/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

1
Serial
data
Start
bit
0 D0
Data
Parity Stop Start
bit bit bit
D1 D7 0/1 1 0 D0
Data
Parity Stop
bit bit
1
D1 D7 0/1 1 ^Idling
(marking)
TDRE
TEND
TXI TXI interrupt
interrupt handler writes
request data in TDR
and clears
TDRE to 0
TXI interrupt
request
1 frame
TEI interrupt request
Figure 15.6 SCI Transmit Operation in Asynchronous Mode
(Example: 8-Bit Data with Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figures 15.7 and 15.8 show a sample flowchart
for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart).
Rev. 3.0, 09/04, page 496 of 1086