SH7058 Datasheet, PDF (733/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

18.6 Appendices
18.6.1 On-Chip Peripheral Module Registers
(1) Address
On-chip peripheral module register addresses and bit names related to the multi-trigger A/D are
shown in table 18.5. 16-bit and 32-bit registers are shown in two and four rows of 8 bits,
respectively.
Table 18.5 Address
Address
Register
Abbr.
Bit 7
Bit 6
Bit 5
Bit Names
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
H'FFFFF720 PAIOR PA15IOR PA14IOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR Port A
H'FFFFF721
PA7IOR PA6IOR PA5IOR PA4IOR PA3IOR PA2IOR PA1IOR PA0IOR
H'FFFFF722 PACRH —
PA15MD —
PA14MD —
PA13MD —
PA12MD
H'FFFFF723
PM11MD1 PA11MD0 PM10MD1 PA10MD0 PM9MD1 PA9MD0 PM8MD1 PA8MD0
H'FFFFF724 PACRL —
PA7MD —
PA6MD —
PA5MD —
PA4MD
H'FFFFF725
—
PA3MD —
PA2MD —
PA1MD —
PA0MD
H'FFFFF726 PADR PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR
H'FFFFF727
PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR
(2) Register States in Reset and Power-Down States
Table 18.6 Register States in Reset and Power-Down States
Type
Multi-trigger A/D
(MTAD)
Name
ADTCR0, ADTCR1
ADTSR0, ADTSR1
ADTIER0, ADTIER1
ADCNT0, ADCNT1
ADGR0A, ADGR0B
ADGR1A, ADGR1B
ADCYLR0, ADCYLR1
ADDR0A, ADDR0B
ADDR1A, ADDR1B
Reset State Power-Down State
Hardware Software
Power-On Standby Standby
Initialized Initialized Initialized
Sleep
Held
Rev. 3.0, 09/04, page 692 of 1086