SH7058 Datasheet, PDF (472/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match
between the GR11A and TCNT11 values.
12.3 Operation
12.3.1 Overview
APC pulse output is enabled by designating multiplex pins for APC pulse output with the pin
function controller (PFC), and setting the corresponding bits to 1 in the pulse output port control
register (POPCR).
When general register 11A (GR11A) in the advanced timer unit II (ATU-II) subsequently
generates a compare-match signal, 1 is output from the pins set to 1 by bits 7 to 0 in POPCR.
When general register 11B (GR11B) generates a compare-match signal, 0 is output from the pins
set to 1 by bits 15 to 8 in POPCR.
0 is output from the output-enabled state until the first compare-match occurs.
The advanced pulse controller output operation is shown in figure 12.2.
CR
Upper 8 bits
of POPCR
Compare-match
signal
GR11B
APC output pins
(PULS0 to PULS7)
Port function
selection
Reset signal
Set signal
Compare-match
signal
GR11A
Lower 8 bits
of POPCR
Figure 12.2 Advanced Pulse Controller Output Operation
Rev. 3.0, 09/04, page 431 of 1086