SH7058 Datasheet, PDF (623/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Note: It is recommended that the timer should be disabled (TCR15 = 0) to change the setting of
the registers related to the timer.
16.6.1 Timer Counter Register n (TCNTRn) (n = 0, 1)
The timer counter register (TCNTR) is a 16-bit readable/writable register that allows the CPU to
monitor and modify the value of the free-running timer counter. When the timer matches TCMR0
(timer compare match register 0) and TCR11 is set to 1, TCNTR is set to LOSR (local offset
register) and counting starts again.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCNTR[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name
Initial Value R/W Description
15 to 0 TCNTR[15:0] 0
R/W* Indicate the value of the free-running timer.
Note: * This register is cleared by the compare match condition.
Rev. 3.0, 09/04, page 582 of 1086