SH7058 Datasheet, PDF (420/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Pφ
TCNT3
Clock
TCNT3 0000
Compare-match
trigger
(from channel 9)
GR3A
0001
0002
0003
0004
0005
0003
5678
5679
567A
567B
567C
567D
567E
567A
TSR3
IMF3A
Cleared by software
Figure 11.25 Event Cycle Measurement Operation
11.3.12 Channel 10 Functions
Inter-Edge Measurement Function and Edge Input Cessation Detection Function:32-bit input
capture register 10A (ICR10A) and 32-bit output compare register 10A (OCR10A) in channel 10
unconditionally perform input capture and compare-match operations, respectively. These
registers are connected to 32-bit free-running counter TCNT10A.
When the corresponding bit is set in the timer start register (TSTR), the entire channel 10 starts
operating. ICR10A has an external input pin (TI10), and when an edge is input at this input pin,
ICR10A captures the TCNT10A value. At this time, TCNT10A is cleared to H'00000001. The
captured value is transferred to the read register (RLD10C) in the multiplied clock generation
block. By making the appropriate setting in the interrupt enable register (TIER), an interrupt
request can be sent to the CPU. This allows inter-edge measurement to be carried out.
When TCNT10A reaches the value set in OCR10A, a compare-match interrupt can be requested.
In this way it is possible to detect the cessation of edge input beyond the time set in OCR10A.
The input edge from TI10 is synchronized internally; the internal signal is AGCK. Noise
cancellation is possible for edges input at TI10 using the timer 10H (TCNT10H) input cancellation
function by setting the NCE bit in timer control register TCR10. When an edge is input at TI10,
TCNT10H starts and input is disabled until it reaches compare-match register NCR10.
Edge input operation without noise cancellation is shown in figure 11.26, edge input operation
with noise cancellation in figure 11.27, and TCNT10A capture operation and compare-match
operation in figure 11.28.
Rev. 3.0, 09/04, page 379 of 1086