SH7058 Datasheet, PDF (545/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Receiving Multiprocessor Serial Data: Figure 15.13 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is as follows (the
steps correspond to the numbers in the flowchart):
Initialization
1
Start of reception
Set MPIE bit in SCR to 1
2
Read ORER and FER bits in SSR
FER = 1?
Yes
or ORER =1?
No
Read RDRF bit in SSR
3
No
RDRF = 1?
Yes
Read receive data from RDR
No
Is ID the station’s ID?
Yes
Read ORER and FER bits in SSR
FER = 1?
Yes
or ORER =1?
No
Read RDRF bit in SSR
5
No
RDRF = 1?
Yes
Read receive data from RDR
No
All data received?
Yes
Clear RE bit in SCR to 0
End of reception
1. SCI initialization: Set the RxD pin using the
PFC.
2. ID receive cycle: Set the MPIE bit in the
serial control register (SCR) to 1.
3. SCI status check and compare to ID
reception: Read the serial status register
(SSR), check that RDRF is set to 1, then
read data from the receive data register
(RDR) and compare with the processor’s
own ID. If the ID does not match the receive
data, set MPIE to 1 again and clear RDRF
to 0. If the ID matches the receive data,
clear RDRF to 0.
4. Receive error handling and break detection:
If a receive error occurs, read the ORER
and FER bits in SSR to identify the error.
After executing the necessary error
handling, clear both ORER and FER to 0.
Receiving cannot resume if ORER or FER
remain set to 1. When a framing error
occurs, the RxD pin can be read to detect
the break state.
5. SCI status check and data receiving: Read
SSR, check that RDRF is set to 1, then
read data from the receive data register
(RDR).
4
Error handling
Figure 15.13 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
Rev. 3.0, 09/04, page 504 of 1086