SH7058 Datasheet, PDF (175/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

UBARH/UBARL
UBAMRH/UBAMRL
Internal address
bits 31–0
32
32
CP1 CP0
32
32
32
CPU cycle
DMA cycle
ID1 ID0
Instruction fetch
Data access
RW1 RW0
Read cycle
Write cycle
SZ1 SZ0
User
break
interrupt
Byte size
Word size
Longword size
UBID
Figure 8.2 Break Condition Judgment Method
Rev. 3.0, 09/04, page 134 of 1086