SH7058 Datasheet, PDF (842/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

• Bit 0—PL0 Mode Bit (PL0MD): Selects the function of pin PL0/TI10.
Bit 0: PL0MD
0
1
Description
General input/output (PL0)
ATU-II edge input (TI10)
(Initial value)
21.3.25 Port L Invert Register (PLIR)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
— PL9IR PL8IR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit: 7
6
5
4
3
2
1
0
PL7IR —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
The port L invert register (PLIR) is a 16-bit readable/writable register that sets the port L inversion
function. Bits PL9IR to PL7IR correspond to pins PL9/SCK4/IRQ5 to PL7/SCK2. PLIR is
enabled when port L pins function as serial clock pins, and disabled otherwise.
When port L pins function as serial clock pins, the value of a pin is inverted when the
corresponding bit in PLIR is set to 1.
PLIR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
PLnIR
0
1
n = 9 to 7
Description
Value is not inverted
Value is inverted
(Initial value)
Rev. 3.0, 09/04, page 801 of 1086