SH7058 Datasheet, PDF (1035/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

27.3.11 H-UDI Timing
Table 27.16 shows H-UDI timing.
Table 27.16 H-UDI Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 125°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing on-chip flash memory, T_a = –40°C to 85°C.
Item
Symbol Min
Max
Unit Figures
TCK clock cycle
TCK clock high-level width
TCK clock low-level width
TRST pulse width
TRST setup time
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO delay time 1
TDO delay time 2
t_tcyc
2
—
t_tcyc
Figure 27.21
t
TCKH
0.4
0.6
t
tcyc
t_TCKL
0.4
0.6
t_tcyc
t_TRSW
20
—
t_cyc
Figure 27.22
t_TRSS
30
—
ns
t_TMSS
30
—
ns
Figure 27.23
t_TMSH
10
—
ns
t_TDIS
30
—
ns
t_TDIH
10
—
ns
t_TDOD1
—
30
ns
t_TDOD2
—
30
ns
Figure 27.24
[Operating precautions]
The H-UDI pins constitute a circuit requiring the voltage of V_CC = 3.3 V ±0.3 V. Comply with the
input and output voltages specified in the DC characteristics, for operation.
TCK
t_TCKH
t_TCKL
V_IH
V_IH
V_IL
t_tcyc
V_IH
V_IL
Figure 27.21 H-UDI Clock Timing
Rev. 3.0, 09/04, page 994 of 1086