SH7058 Datasheet, PDF (572/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Register Name
MBx[4], MBx[5]*
Address
Bit
H'104 + N×32 13
Bit Name
NMC
Note: * x/N: 0 to 31 (Indicates the mailbox number)
Description
New Message Control
When this bit is cleared, a mailbox in
which PXPR/PFPR has been already set
does not store the new message but
retains the previous one and sets the
UMSR corresponding bit.
When this bit is set, a mailbox in which
PXPR/PFPR has been already set stores
the new message and sets the UMSR
corresponding bit.
If a message is received in a mailbox in
overwrite mode (NMC = 1), the host CPU
must perform an additional check at the
end of the data reading from the mailbox
in order to guarantee that the mailbox
data have not been corrupted during
such operation by another receive
message. The additional check, to be
performed at the end of the mailbox
access, consists in verifying that the
associated bit of UMSR has not been set
and so no overwrite has occurred; in
case such bit is set data have been
corrupted and so the message must be
discarded.
Rev. 3.0, 09/04, page 531 of 1086