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SH7058 Datasheet, PDF (353/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine
11.2.9 Timer Mode Register (TMDR)
The timer mode register (TMDR) is an 8-bit register. The ATU-II has one TDR register.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— T5PWM T4PWM T3PWM
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
TMDR is an 8-bit readable/writable register that specifies whether channels 3 to 5 are used in
input capture/output compare mode or PWM mode.
TMDR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 2—PWM Mode 5 (T5PWM): Selects whether channel 5 operates in input capture/output
compare mode or PWM mode.
Bit 2: T5PWM
0
1
Description
Channel 5 operates in input capture/output compare mode
Channel 5 operates in PWM mode
(Initial value)
When bit T5PWM is set to 1 to select PWM mode, pins TIO5A to TIO5C become PWM
output pins, general register 5D (GR5D) functions as a cycle register, and general registers 5A
to 5C (GR5A to GR5C) function as duty registers. Settings in the timer I/O control registers
(TIOR5A, TIOR5B) are invalid, and general registers 5A to 5D (GR5A to GR5D) can be
written to. Do not use the TIO5D pin as a timer output.
• Bit 1—PWM Mode 4 (T4PWM): Selects whether channel 4 operates in input capture/output
compare mode or PWM mode.
Bit 1: T4PWM
0
1
Description
Channel 4 operates in input capture/output compare mode
Channel 4 operates in PWM mode
(Initial value)
When bit T4PWM is set to 1 to select PWM mode, pins TIO4A to TIO4C become PWM
output pins, general register 4D (GR4D) functions as a cycle register, and general registers 4A
to 4C (GR4A to GR4C) function as duty registers. Settings in the timer I/O control registers
(TIOR4A, TIOR4B) are invalid, and general registers 4A to 4D (GR4A to GR4D) can be
written to. Do not use the TIO4D pin as a timer output.
Rev. 3.0, 09/04, page 312 of 1086