SH7058 Datasheet, PDF (100/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

From any state
when
=0
and
=1
Power-on reset state
=0
=1
When an interrupt source
or DMA address error occurs
=1
Exception processing state
Bus request
cleared
Bus request
generated
Bus release state
Exception
processing
source occurs
NMI interrupt
source occurs
Exception
processing
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
SBY bit
cleared
for SLEEP
instruction
Program execution state
SBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Hardware standby mode
Power-down state
From any state when
= 0 and
=0
Note: An internal reset due to the WDT causes a transition from the program execution state
or sleep mode to the exception processing state.
Figure 2.8 Transitions between Processing States
Rev. 3.0, 09/04, page 59 of 1086