SH7058 Datasheet, PDF (607/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

16.5.1 Transmit Pending Request Register n (TXPR0n, TXPR1n) (n = 0, 1)
TXPR1 and TXPR0 are 16-bit readable/conditionally-writable registers that contain any transmit
wait flags for the CAN module. TXPR1 controls mailbox 31 to mailbox 16, and TXPR0 controls
mailbox 15 to mailbox 1. The host CPU makes a transmit message stored in a mailbox be in a
transmit wait state by writing 1 to the corresponding bit. Writing 0 is ignored, and TXPR cannot
be cleared by writing 0 and must be cleared by setting the corresponding TXCR bits. TXPR may
be read by the host CPU to determine which, if any, transmissions are waiting. There is a transmit
wait bit for all mailboxes except for mailbox 0. Writing 1 to a bit when the mailbox is set for
reception is ignored, and TXPR is automatically cleared when an internal arbitration for
transmission runs.
The HCAN will clear a transmit wait flag after successful transmission of its corresponding
message or when a transmission wait cancellation is requested successfully from TXCR. TXPR is
not cleared if the message is not transmitted due to the CAN node losing the arbitration processing
or due to errors on the CAN bus, and the HCAN automatically tries to transmit it again unless its
DART bit (disable automatic re-transmission) is set in the message control of the corresponding
mailbox. In such case (DART set) the transmission wait is cleared and notified through mailbox
empty interrupt flag (IRR8) and the correspondent bit in the abort acknowledgement register
(ABACK).
If the status of TXPR changes, the HCAN shall ensure that in the ID priority scheme (MCR[2] =
0), the highest priority message is always presented for transmission in an intelligent way even
under circumstances such as bus arbitration losses or errors on the CAN bus. For details, see
section 16.7, Operation.
When the HCAN changes the state of any TXPR bit to 0, a mailbox empty interrupt (IRR8) may
be generated. This indicates that either a successful or an aborted mailbox transmission has just
been made. If a message transmission is successful, it is indicated in TXACK, and if a message
transmission abortion is successful, it is indicated in ABACK. By checking these registers, the
contents of the message data of the corresponding mailbox is modified to prepare for the next
transmission.
Important: If mailbox 31 is used as a transmit buffer, there is a usage limitation. For details, see
section 16.8, Usage Notes.
Rev. 3.0, 09/04, page 566 of 1086