SH7058 Datasheet, PDF (913/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

In the download processing, the values of the general registers of the CPU are retained.
During the download processing, the interrupt processing cannot be executed. However, the
NMI, UBC, and H-UDI interrupt requests are retained, so that on returning to the user
procedure program, the interrupt processing starts. For details on the relationship between
download and interrupts, see section 23.8.2, Interrupts during Programming/Erasing.
Since a stack area of maximum 128 bytes is used, an area of at least 128 bytes must be saved
before setting the SCO bit to 1.
If an access by the DMAC or AUD occurs during download, operation cannot be guaranteed.
Therefore, access by the DMAC or AUD must not be executed.
(2.4) FKEY is cleared to H'00 for protection.
(2.5) The value of the DPFR parameter must be checked to confirm the download result.
A recommended procedure for confirming the download result is shown below.
• Check the value of the DPFR parameter (one byte of start address of the download
destination specified by FTDAR). If the value is H’00, download has been performed
normally. If the value is not H’00, the source that caused download to fail can be
investigated by the description below.
• If the value of the DPFR parameter is the same as before downloading (e.g. H’FF), the
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
• If the value of the DPFR parameter is different from before downloading, check the SS
bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download
program selection and FKEY register setting were normal, respectively.
(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is
set to the FUBRA parameter for initialization.
• The current frequency of the CPU clock is set to the FPEFEQ parameter (general
register R4). For the settable range of the FPEFEQ parameter, see section 27.3.2, Clock
Timing.
For the settable range of the FPEFEQ parameter, see section 27.3.2, Clock Timing.
When the frequency is set out of this range, an error is returned to the FPFR parameter
of the initialization program and initialization is not performed. For details on the
frequency setting, see the description in 23.4.3 (2.1) Flash programming/erasing
frequency parameter (FPEFEQ).
Rev. 3.0, 09/04, page 872 of 1086