SH7058 Datasheet, PDF (297/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

11.2.5 Timer Status Registers (TSR)
The timer status registers (TSR) are 16-bit registers. The ATU-II has 11 TSR registers: one each
for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5. For
details of channel 10, see section 11.2.26, Channel 10 Registers.
Channel
0
1
2
3
4
5
6
7
8
9
11
Abbreviation
TSR0
TSR1A, TSR1B
TSR2A, TSR2B
TSR3
Function
Indicates input capture, interval interrupt, and overflow status
Indicate input capture, compare-match, and overflow status
Indicates input capture, compare-match, and overflow status
TSR6
TSR7
TSR8
TSR9
TSR11
Indicate cycle register compare-match status
Indicates down-counter output end (low) status
Indicates event counter compare-match status
Indicates input capture, compare-match, and overflow status
The TSR registers are 16-bit readable/writable registers containing flags that indicate free-running
counter (TCNT) overflow, channel 0 input capture or interval interrupt generation, channel 3, 4, 5,
and 11 general register input capture or compare-match, channel 6 and 7 compare-matches,
channel 8 down-counter output end, and channel 9 event counter compare-matches.
Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is
enabled by the corresponding bit in the timer interrupt enable register (TIER).
Each TSR is initialized to H'0000 by a power-on reset, and in hardware standby mode and
software standby mode.
Rev. 3.0, 09/04, page 256 of 1086