SH7058 Datasheet, PDF (564/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

(5) CAN Interface
The CAN interface supports the requirements for a CAN bus data link controller which is
specified in Reference 2 (section 16.1). It fulfils all the functions of a data link layer (DLC
layer) as specified by the 7 layers of the OSI model. This block provides the receive error
counter, transmit error counter, and bit timing set registers, and various test modes
corresponding to the CAN bus specification. This block also stores transmit/receive data for
the CAN data link controller.
16.2.3 Pin Configuration
Table 16.1 lists the pin configuration and functions.
Table 16.1 Pin Configuration
Name
HRxD0
HTxD0
HRxD1
HTxD1
Input/Output
Input
Output
Input
Output
Function
CAN bus receive signal of channel 0
CAN bus transmit signal of channel 0
CAN bus receive signal of channel 1
CAN bus transmit signal of channel 1
16.2.4 Memory Map
Figures 16.2 (1) and 16.2 (2) show the memory maps of registers which can be accessed by
software.
Base address: Channel 0 → H'FFFFD000, channel 1 → H'FFFFD800
Rev. 3.0, 09/04, page 523 of 1086