SH7058 Datasheet, PDF (543/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Initialization
1
Start of transmission
Read TDRE bit in SSR
2
No
TDRE = 1?
Yes
Write transmit data in TDR
and set MPBT in SSR
Clear TDRE bit to 0
No
All data transmitted?
Yes
Read TEND bit in SSR
TEND = 1?
No
1. SCI initialization: Set the TxD pin using the
PFC. After the TE bit is set to 1, a frame of
1s is output, and transmission is enabled.
2. SCI status check and transmit data write:
Read the serial status register (SSR), check
that the TDRE bit is 1, then write transmit
data in the transmit data register (TDR).
Also set MPBT (multiprocessor bit transfer)
to 0 or 1 in SSR. Finally, clear TDRE to 0.
3. Continue transmitting serial data: Read the
TDRE bit to check whether it is safe to write
(if it reads 1); if so, write data in TDR, then
clear TDRE to 0. When the DMAC is started
by a transmit-data-empty interrupt request
3
(TXI) to write data in TDR, the TDRE bit is
checked and cleared automatically.
4. Output a break at the end of serial
transmission: Set the data register (DR) of
the port to 0, then clear TE to 0 in SCR and
set the TxD pin function as output port with
the PFC.
Yes
Output break signal?
Yes
Clear port DR to 0
No
4
Clear TE bit in SCR to 0;
select theTxD pin function as
an output port with the PFC
End of transmission
Figure 15.11 Sample Flowchart for Transmitting Multiprocessor Serial Data
Rev. 3.0, 09/04, page 502 of 1086