SH7058 Datasheet, PDF (127/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 6.1 Types of Exception Processing and Priority Order (cont)
Exception Source
Priority
InstructionsTrap instruction (TRAPA instruction)
High
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay branch
instruction*¹ or instructions that rewrite the PC*²)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF.
6.1.2 Exception Processing Operations
The exception processing sources are detected and begin processing according to the timing
shown in table 6.2.
Table 6.2 Timing of Exception Source Detection and Start of Exception Processing
Exception Source
Reset
Power-on reset
Manual reset
Address error
Interrupts
Instructions
Trap instruction
General illegal
instructions
Illegal slot
instructions
Floating point
instructions
Timing of Source Detection and Start of Processing
Starts when the RES pin changes from low to high or when the
WDT overflows.
Starts when the WDT overflows.
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Starts from the execution of a TRAPA instruction.
Starts from the decoding of undefined code anytime except
after a delayed branch instruction (delay slot).
Starts from the decoding of undefined code placed in a
delayed branch instruction (delay slot) or of instructions that
rewrite the PC.
Starts when a floating-point instruction causes an invalid
operation exception (IEEE754 specification) or division-by-zero
exception.
Rev. 3.0, 09/04, page 86 of 1086