SH7058 Datasheet, PDF (488/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

13.3.4 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip (figure 13.7).
CK
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 13.7 Timing of Setting WOVF
13.4 Usage Notes
13.4.1 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT,
the write takes priority and the timer counter is not incremented (figure 13.8).
Rev. 3.0, 09/04, page 447 of 1086