SH7058 Datasheet, PDF (974/1130 Pages) Renesas Technology Corp – Renesas SuperHTM RISC engine

Table 23.28 Stipulated Transition Times to Command Wait State
Condition: V_CC = 3.3 V ± 0.3 V, V_SS = 0 V, T_a = 25°C ± 5°C
Code
Standby release
(oscillation stabilization
time)
Programmer mode setup
time
V_CC hold time
Symbol Min
t
30
osc1
t_bmv
10
t_dwn
0
Max
Unit
ms
ms
ms
Note
V_CC
tosc1
Memory read mode
tbmv ^{Command wait state}
Auto-program mode
Auto-erase mode
Command wait state
Normal/abnormal
end identification _tdwn
FWE
Note: Set the FWE input pin to low level, except in the auto-program and auto-erase modes.
Figure 23.39 Oscillation Stabilization Time, Programmer Mode Setup Time, and Power-
Down Sequence
23.10.3 Storable Area for Procedure Program and Programming Data
In the descriptions in the previous section, storable areas for the programming/erasing procedure
programs and program data are assumed to be in on-chip RAM. However, the procedure
programs and data can be stored in and executed from other areas (e.g. external address space) as
long as the following conditions are satisfied.
(1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in
on-chip RAM, therefore, this area is not available for use.
(2) The on-chip programming/erasing program will use 128 bytes or more as a stack. Make sure
this area is reserved.
(3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be
executed in on-chip RAM.
(4) The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been judged. When in a mode in which the external address space is
not accessible, such as single-chip mode, the required procedure programs, interrupt vector
Rev. 3.0, 09/04, page 933 of 1086