SH7032 Datasheet, PDF (94/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Interrupt Controller (INTC)
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Input
control
UBC
DMAC
ITU
SCI
PRT
A/D
WDT
REF
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
decision
logic
Com-
parator
Interrupt request
SR
I3 I2 I1 I0
CPU
IPR
ICR
IPRA–IPRE
Module bus
Bus
interface
UBC: User break controller
DMAC: Direct memory access controller
ITU: 16-bit integrated timer pulse unit
SCI: Serial communication interface
PRT: Parity control unit of BSC
A/D: A/D converter
INTC
WDT: Watchdog timer
REF: DRAM refresh control unit of BSC
ICR: Interrupt control register
IPRA-IPRE: Interrupt priority registers A-E
SR: Status register
Figure 5.1 Block Diagram of Interrupt Controller
Rev. 7.00 Jan 31, 2006 page 68 of 658
REJ09B0272-0700