SH7032 Datasheet, PDF (16/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8.1.1 Features................................................................................................................ 103
8.1.2 Block Diagram..................................................................................................... 104
8.1.3 Pin Configuration................................................................................................. 105
8.1.4 Register Configuration......................................................................................... 106
8.1.5 Overview of Areas ............................................................................................... 107
8.2 Register Descriptions ........................................................................................................ 109
8.2.1 Bus Control Register (BCR) ................................................................................ 109
8.2.2 Wait State Control Register 1 (WCR1)................................................................ 111
8.2.3 Wait State Control Register 2 (WCR2)................................................................ 113
8.2.4 Wait State Control Register 3 (WCR3)................................................................ 115
8.2.5 DRAM Area Control Register (DCR).................................................................. 117
8.2.6 Refresh Control Register (RCR) .......................................................................... 119
8.2.7 Refresh Timer Control/Status Register (RTCSR) ................................................ 121
8.2.8 Refresh Timer Counter (RTCNT)........................................................................ 122
8.2.9 Refresh Time Constant Register (RTCOR) ......................................................... 123
8.2.10 Parity Control Register (PCR) ............................................................................. 124
8.2.11 Notes on Register Access..................................................................................... 126
8.3 Address Space Subdivision ............................................................................................... 127
8.3.1 Address Spaces and Areas ................................................................................... 127
8.3.2 Bus Width ............................................................................................................ 129
8.3.3 Chip Select Signals (CS0–CS7) ........................................................................... 129
8.3.4 Shadows ............................................................................................................... 130
8.3.5 Area Descriptions................................................................................................. 132
8.4 Accessing External Memory Space .................................................................................. 139
8.4.1 Basic Timing........................................................................................................ 139
8.4.2 Wait State Control................................................................................................ 141
8.4.3 Byte Access Control ............................................................................................ 144
8.5 DRAM Interface Operation............................................................................................... 145
8.5.1 DRAM Address Multiplexing.............................................................................. 145
8.5.2 Basic Timing........................................................................................................ 147
8.5.3 Wait State Control................................................................................................ 149
8.5.4 Byte Access Control ............................................................................................ 151
8.5.5 DRAM Burst Mode.............................................................................................. 153
8.5.6 Refresh Control.................................................................................................... 158
8.6 Address/Data Multiplexed I/O Space Access ................................................................... 162
8.6.1 Basic Timing........................................................................................................ 162
8.6.2 Wait State Control................................................................................................ 163
8.6.3 Byte Access Control ............................................................................................ 164
8.7 Parity Check and Generation ............................................................................................ 164
8.8 Warp Mode ....................................................................................................................... 165
Rev. 7.00 Jan 31, 2006 page xvi of xxvi