SH7032 Datasheet, PDF (19/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10.6.7 Contention Between Counter Clearing by Input Capture and
Counter Increment................................................................................................ 300
10.6.8 Contention between General Register Write and Input Capture .......................... 301
10.6.9 Note on Waveform Cycle Setting ........................................................................ 301
10.6.10 Contention between BR Write and Input Capture................................................ 302
10.6.11 Note on Writing in Synchronizing Mode............................................................. 303
10.6.12 Note on Setting Reset-Synchronized PWM Mode/Complementary
PWM Mode.......................................................................................................... 303
10.6.13 Clearing Complementary PWM Mode ................................................................ 304
10.6.14 Note on Counter Clearing by Input Capture ........................................................ 304
10.6.15 ITU Operating Modes .......................................................................................... 305
Section 11 Programmable Timing Pattern Controller (TPC).................................. 313
11.1 Overview........................................................................................................................... 313
11.1.1 Features ................................................................................................................ 313
11.1.2 Block Diagram ..................................................................................................... 314
11.1.3 Input/Output Pins ................................................................................................. 315
11.1.4 Registers............................................................................................................... 316
11.2 Register Descriptions ........................................................................................................ 317
11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2)............................................ 317
11.2.2 Port B Data Register (PBDR) .............................................................................. 318
11.2.3 Next Data Register A (NDRA) ............................................................................ 318
11.2.4 Next Data Register B (NDRB)............................................................................. 320
11.2.5 Next Data Enable Register A (NDERA).............................................................. 322
11.2.6 Next Data Enable Register B (NDERB) .............................................................. 322
11.2.7 TPC Output Control Register (TPCR) ................................................................. 323
11.2.8 TPC Output Mode Register (TPMR) ................................................................... 325
11.3 Operation........................................................................................................................... 326
11.3.1 Overview.............................................................................................................. 326
11.3.2 Output Timing...................................................................................................... 327
11.3.3 Examples of Use of Ordinary TPC Output .......................................................... 328
11.3.4 TPC Output Non-Overlap Operation ................................................................... 331
11.3.5 TPC Output by Input Capture .............................................................................. 335
11.4 Usage Notes ...................................................................................................................... 336
11.4.1 Non-Overlap Operation........................................................................................ 336
Section 12 Watchdog Timer (WDT).............................................................................. 339
12.1 Overview........................................................................................................................... 339
12.1.1 Features ................................................................................................................ 339
12.1.2 Block Diagram ..................................................................................................... 340
Rev. 7.00 Jan 31, 2006 page xix of xxvi