SH7032 Datasheet, PDF (599/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Table A.7 SSR Bit Functions
Bit Bit name
Value Description
7 Transmit data 0
register
empty
(TDRE)
1
Indicates that valid transmit data has been written to TDR
Clear Conditions: (1) 0 written in TDRE after reading TDRE = 1; (2)
Data written to TDR by DMAC
Indicates that there is no valid transmit data in TDR (Initial value)
Set Conditions: (1) Reset or standby mode; (2) TE bit of SCR is 0;
(3) Data transferred to TSR from TDR and data writing to TDR
enabled
6 Receive data 0
register full
(RDRF)
Indicates that there is no valid receive data stored in RDR
(Initial value)
Clear Conditions: (1) Reset or standby mode; (2) 0 written in RDRF
after reading RDRF = 1; (3) Data read in RDR by DMAC
1
Indicates that valid receive data is stored in RDR
Set Conditions: Serial reception ends normally and receive data is
transferred to RDR from RSR
5 Overrun error 0
(ORER)
Indicates that reception is in progress or has ended normally
(Initial value)
Clear Conditions: (1) Reset or standby mode; (2) 0 written in ORER
after reading ORER = 1
1
Indicates that an overrun error occurred in reception
Set Conditions: The next serial reception ends while RDRF = 1
4 Framing error 0
(FER)
Indicates that reception is in progress or has ended normally
(Initial value)
Clear Conditions: (1) Reset or standby mode; (2) 0 written in FER
after reading FER = 1
1
Indicates that a framing error occurred in reception
Set Conditions: When the stop bit at the end of the receive data
when the SCI finishes receiving has been checked to see if it is 1
and the stop bit is 0
3 Parity error 0
(PER)
Indicates that reception is in progress or has ended normally
(Initial value)
Clear Conditions: (1) Reset or standby mode; (2) 0 written in PER
after reading PER = 1
1
Indicates that a parity error occurred in reception
Set Conditions: When the number of 1’s in the receive data and
parity bit together during reception is not consistent with the
even/odd parity setting specified in the O/E bit of the serial mode
register (SMR)
Rev. 7.00 Jan 31, 2006 page 573 of 658
REJ09B0272-0700