SH7032 Datasheet, PDF (185/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
refresh is performed when they match. RTCNT is simultaneously cleared to H'00 and
incrementing begins again.
When the clock is selected with the CKS2–CKS0 bits, RTCNT immediately begins to increment
from its current value. This means that when the RTCOR cycle is set after the CKS2–CKS0 bits
are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the
RTCNT will overflow once (from H'FF to H'00) and incrementing will start again. Since the CBR
refresh will not be performed until the RTCNT again matches the RTCOR value, the initial refresh
interval will be rather long. It is thus advisable to set the RTCOR cycle prior to setting the CKS2–
CKS0 bits and start it incrementing. When CBR refresh control is being performed after use as an
8-bit interval timer, the RTCNT count value may be in excess of the refresh cycle. For this reason,
clear RTCNT by writing H'00 before starting refresh control to assure a correct refresh interval.
When the RW1 bit in WCR1 is set to 1 and the read cycle is set to long pitch, the number of wait
states selected by the RLW1 and RLW0 bits in RCR will be inserted into the CBR refresh cycle,
regardless of the status of the WAIT signal. Figure 8.29 shows RTCNT operation and figure 8.30
shows the timing of the CBR refresh. For details on timing, see sections 20.1.3 (3) and 20.2.3 (3),
Bus Timing.
RTCNT
value
RTCOR
value
Compare
match
with RTCOR
Compare
match
with RTCOR
Compare
Compare
match
match
with RTCOR with RTCOR
H'00
Time
Clock
CBR
selected with
CKS2–CKS0
CBR
CBR
CBR: CAS-before-RAS refresh
CBR
Figure 8.29 Refresh Timer Counter (RTCNT) Operation
T_Rp
T_Rr
T_Rc
CK
RAS
CAS
Figure 8.30 Output Timing for CAS-Before-RAS Refresh Signal
Rev. 7.00 Jan 31, 2006 page 159 of 658
REJ09B0272-0700