SH7032 Datasheet, PDF (231/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
CK
A21–A0
CSn
D15–D0
Source address Destination address
RD
WRH
WRL
DACK
Figure 9.9 DMA Transfer Timing in Dual Address Mode (External Memory Space to
External Memory Space Transfer with DACK Output in Read Cycle)
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode with the TM bits in
CHCR0–CHCR3.
• Cycle-Steal Mode
In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (word or
byte) DMA transfer. When another transfer request occurs, the bus is obtained from the other
bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus is
passed to the other bus master. This is repeated until the transfer end conditions are satisfied.
Cycle-steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 9.10 shows an example of DMA transfer timing in cycle-steal mode.
Transfer conditions shown in the figure are:
 Dual address mode
 DREQ level detection
DREQ
Bus returned to CPU
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
Figure 9.10 Transfer Example in Cycle-Steal Mode (Dual Address Mode, DREQ Level
Detection)
Rev. 7.00 Jan 31, 2006 page 205 of 658
REJ09B0272-0700