SH7032 Datasheet, PDF (56/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Instruction Format
d format
15
xxxx xxxx dddd
0
dddd
d12 format
15
xxxx dddd
nd8 format
15
xxxx nnnn
i format
dddd
dddd
0
dddd
0
dddd
Source Operand
dddddddd: GBR
indirect with
displacement
Destination
Operand
R0 (Register
direct)
Example
MOV.L
@(disp,GBR),R0
R0 (Register direct) dddddddd: GBR
indirect with
displacement
dddddddd: PC
relative with
displacement
R0 (Register
direct)
dddddddd: PC
—
relative
dddddddddddd: —
PC relative
MOV.L
R0,@(disp,GBR)
MOVA
@(disp,PC),R0
BF
label
BRA label
(label = disp + PC)
dddddddd: PC
relative with
displacement
nnnn: Register
direct
MOV.L
@(disp,PC),Rn
iiiiiiii:
Immediate
Indexed GBR
indirect
AND.B
#imm,@(R0,GBR)
15
0
xxxx xxxx i i i i i i i i
iiiiiiii:
Immediate
R0 (Register
direct)
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii:
Immediate
iiiiiiii:
Immediate
—
nnnn: Register
direct
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
AND #imm,R0
TRAPA #imm
ADD #imm,Rn
Rev. 7.00 Jan 31, 2006 page 30 of 658
REJ09B0272-0700