SH7032 Datasheet, PDF (328/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6.10 Contention between BR Write and Input Capture
When a buffer register (BR) is being used as an input capture register and an input capture signal
is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write.
The timing is shown in figure 10.66.
BR write cycle
T1
T2
T3
CK
Address
Internal
write signal
Input capture
signal
BR address
GR
N
X
BR
M
TCNT value
N
Figure 10.66 Contention between BR Write and Input Capture
Rev. 7.00 Jan 31, 2006 page 302 of 658
REJ09B0272-0700