SH7032 Datasheet, PDF (261/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bit 3—Count Start 3 (STR3): STR3 starts and stops TCNT3.
Bit 3: STR3
0
1
Description
TCNT3 is halted
TCNT3 is counting
(Initial value)
Bit 2—Count Start 2 (STR2): STR2 starts and stops TCNT2.
Bit 2: STR2
0
1
Description
TCNT2 is halted
TCNT2 is counting
(Initial value)
Bit 1—Count Start 1 (STR1): STR1 starts and stops TCNT1.
Bit 1: STR1
0
1
Description
TCNT1 is halted
TCNT1 is counting
(Initial value)
Bit 0—Count Start 0 (STR0): STR0 starts and stops TCNT0.
Bit 0: STR0
0
1
Description
TCNT0 is halted
TCNT0 is counting
(Initial value)
10.2.2 Timer Synchro Register (TSNC)
The timer synchro register (TSNC) is an eight-bit read/write register that selects timer
synchronizing modes for channels 0–4. Channels for which 1 is set in the corresponding bit will be
synchronized. TSNC is initialized to H'E0 or H'60 by a reset and in standby mode.
Bit
7
6
5
4
3
2
1
0
—
—
— SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
Initial value
*
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Note: * Undefined
Rev. 7.00 Jan 31, 2006 page 235 of 658
REJ09B0272-0700