SH7032 Datasheet, PDF (307/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
TCNT4
TCNT3
T
T–1
H' 0000
H' FFFF
Changes prohibited
Figure 10.40 Caution on Changing GR Settings with Buffer Operation (2)
When GR Settings are Outside the Count Range (H'0000–GRA3): Waveforms with a duty
cycle of 0% and 100% can be output by setting GR outside the count area. Be sure to make the
direction of the count (increment/decrement) when writing a setting from outside the count area
into the buffer register (BR) the same as the count direction when writing the setting that returns to
within the count area in BR.
GRA3
GR
H' 0000
0% duty
100% duty
Output pin
Output pin
BR
GR
Write on decrement
Write on increment
Figure 10.41 Example of Changing GR Settings with Buffer Operation (2)
The above settings are made by detecting the occurrence of a GRA3 compare match or underflow
of TCNT4 and then writing to BR. They can also be accomplished by starting the DMAC with a
GRA3 compare match.
Rev. 7.00 Jan 31, 2006 page 281 of 658
REJ09B0272-0700