SH7032 Datasheet, PDF (352/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
Bit 2—Group 2 Non-Overlap Mode (G2NOV): G2NOV selects ordinary or non-overlap mode
for TPC output group 2 (TP11–TP8).
Bit 2: G2NOV
0
1
Description
TPC output group 2 operates normally (output value updated according to
compare match A of the ITU channel selected by TPCR)
(Initial value)
TPC output group 2 operates in non-overlap mode (1 output and 0 output can
be performed independently according to compare match A and B of the ITU
channel selected by TPCR)
Bit 1—Group 1 Non-Overlap Mode (G1NOV): G1NOV selects ordinary or non-overlap mode
for TPC output group 1 (TP7–TP4).
Bit 1: G1NOV
0
1
Description
TPC output group 1 operates normally (output value updated according to
compare match A of the ITU channel selected by TPCR)
(Initial value)
TPC output group 1 operates in non-overlap mode (1 output and 0 output can
be performed independently according to compare match A and B of the ITU
channel selected by TPCR)
Bit 0—Group 0 Non-Overlap Mode (G0NOV): G0NOV selects ordinary or non-overlap mode
for TPC output group 0 (TP3–TP0).
Bit 0: G0NOV
0
1
Description
TPC output group 0 operates normally (output value updated according to
compare match A of the ITU channel selected by TPCR)
(Initial value)
TPC output group 0 operates in non-overlap mode (1 output and 0 output can
be performed independently according to compare match A and B of the ITU
channel selected by TPCR)
11.3 Operation
11.3.1 Overview
When corresponding bits in the PBCR1, PBCR2, NDERA, and NDERB registers are set to 1, TPC
output is enabled and the PBDR data register values are output. After that, when the compare
match event selected by TPCR occurs, the next data register contents (NDRA and NDRB) are
transferred to PBDR and output values are updated. Figure 11.2 illustrates the TPC output
operation.
Rev. 7.00 Jan 31, 2006 page 326 of 658
REJ09B0272-0700