SH7032 Datasheet, PDF (318/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.5.2 Status Flag Clear Timing
The status flags are cleared by being read by the CPU when set to 1, then being written with 0.
This timing is shown in figure 10.57.
TSR write cycle
T1
T2
T3
CK
Address
IMF, OVF
TSR address
Figure 10.57 Timing of Status Flag Clearing
Rev. 7.00 Jan 31, 2006 page 292 of 658
REJ09B0272-0700