SH7032 Datasheet, PDF (170/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
8.4.3 Byte Access Control
The upper byte and lower byte control signals when 16-bit bus width space is being accessed can
be selected from (WRH, WRL, A0) or (WR, HBS, LBS). When the byte access select bit (BAS) in
BCR is set to 1, the WRH, WRL, and A0 pins output WR, LBS, and HBS signals. Figure 8.15
illustrates the control signal output timing in the byte write cycle.
Upper byte access
T1
T2
Lower byte access
T1
T2
CK
A0
BAS = 0 WRH
WRL
HBS
BAS = 1 _LBS
WR
Figure 8.15 Byte Access Control Timing For External Memory Space Access (Write Cycle)
The WRH, WRL system and the HBS, LBS system are available as byte access signals for 16-bit
space in address/data multiplexing space and external memory space.
These strobe signals are assigned to pins in the manner: A0/HBS, WRH/LBS, WRL/WR, and the
BAS bit in the bus control register (BCR) is used to switch specify signal sending.
Note that the byte access signals are strobe signals specifically for byte access to a 16-bit space
and are not to be used for byte access to an 8-bit space. When making an access to an 8-bit space,
use the A0/HBS pin as A0 irrespective of the BAS bit value to use the WRL/WR pin as the WR
pin, and avoid using the WRH/LBS pin.
Rev. 7.00 Jan 31, 2006 page 144 of 658
REJ09B0272-0700