SH7032 Datasheet, PDF (363/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
When a compare match B occurs before the compare match A, the 0 data transfer can be
performed before the 1 data transfer, so a non-overlapping waveform can be output. In such cases,
be sure not to change the NDR contents until the compare match A after the compare match B
occurs (non-overlap period). This can be ensured by writing the next data to NDR in the IMIA
interrupt handling routine. The DMAC can also be started using an IMIA interrupt. However,
these write operations should be performed prior to the next compare match B. The timing is
shown in figure 11.10.
Compare
match A
Compare
match B
NDR
NDR write
NDR write
DR
0 output 0/1 output
0 output 0/1 output
NDR write period
NDR write period
NDR write
disable period
NDR write
disable period
Figure 11.10 Non-Overlap Operation and NDR Write Timing
Rev. 7.00 Jan 31, 2006 page 337 of 658
REJ09B0272-0700