SH7032 Datasheet, PDF (117/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

BARH/BARL
Internal address
bits 31–0
CD1
32
32
CD0
CPU cycle
Section 6 User Break Controller (UBC)
BAMRH/BAMRL
32
32
32
DMA cycle
ID1 ID0
Instruction fetch
Data access
RW1 RW0
Read cycle
User
break
interrupt
Write cycle
SZ1 SZ0
Byte size
Word size
Longword size
Figure 6.2 Break Condition Logic
Rev. 7.00 Jan 31, 2006 page 91 of 658
REJ09B0272-0700