SH7032 Datasheet, PDF (209/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
9.1.4 Register Configuration
Table 9.2 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel
has four control registers. One other control register is shared by all channels.
Table 9.2 DMAC Registers
Chan-
nel Name
Abbrevi-
ation
R/W
Initial
Value
Access
Address*⁴ Size
0
DMA source address register 0 SAR0*³ R/W
Undefined H'5FFFF40 16, 32
DMA destination address
register 0
DAR0*³ R/W
Undefined H'5FFFF44 16, 32
DMA transfer count register 0 TCR0*³ R/W
Undefined H'5FFFF4A 16, 32
DMA channel control register 0 CHCR0 R/(W)*¹ H'0000
H'5FFFF4E 8, 16, 32
1
DMA source address register 1 SAR1*³ R/W
Undefined H'5FFFF50 16, 32
DMA destination address
register 1
DAR1*³ R/W
Undefined H'5FFFF54 16, 32
DMA transfer count register 1 TCR1*³ R/W
Undefined H'5FFFF5A 16, 32
DMA channel control register 1 CHCR1 R/(W)*¹ H'0000
H'5FFFF5E 8, 16, 32
2
DMA source address register 2 SAR2*³ R/W
Undefined H'5FFFF60 16, 32
DMA destination address
register 2
DAR2*³ R/W
Undefined H'5FFFF64 16, 32
DMA transfer count register 2 TCR2*³ R/W
Undefined H'5FFFF6A 16, 32
DMA channel control register 2 CHCR2 R/(W)*¹ H'0000
H'5FFFF6E 8, 16, 32
3
DMA source address register 3 SAR3*³ R/W
Undefined H'5FFFF70 16, 32
DMA destination address
register 3
DAR3*³ R/W
Undefined H'5FFFF74 16, 32
DMA transfer count register 3 TCR3*³ R/W
Undefined H'5FFFF7A 16, 32
DMA channel control register 3 CHCR3 R/(W)*¹ H'0000
H'5FFFF7E 8, 16, 32
Shar- DMA operation register
ed
DMAOR R/(W)*² H'0000
H'5FFFF48 8, 16, 32
Notes: 1. Only 0 can be written in bit 1 of CHCR0–CHCR3, to clear flags.
2. Only 0 can be written in bits 1 and 2 of DMAOR, to clear flags.
3. Access SAR0–SAR3, DAR0–DAR3, and TCR0–TCR3 by longword or word. If byte
access is used when writing, the value of the register contents will be undefined; if used
when reading, the value read will be undefined.
4. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Rev. 7.00 Jan 31, 2006 page 183 of 658
REJ09B0272-0700