SH7032 Datasheet, PDF (237/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
CK
DREQ
Bus cycle
CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: Illustrates the case when DACK is output during the DMAC write cycle.
Figure 9.16 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States)
T1 Tw T2
T1 Tw T2
CK
DREQ
Bus cycle
CPU CPU CPU
DMAC
CPU
DMAC
CPU
DACK
Note: When DREQ is negated at the third state of the DMAC cycle, the next DMA
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
Figure 9.17 DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ Level
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 2 States + 1 Wait
State)
Rev. 7.00 Jan 31, 2006 page 211 of 658
REJ09B0272-0700