SH7032 Datasheet, PDF (518/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 Electrical Characteristics
CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
WR (Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
RD(Write)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
T_p
T_r
T_c1
T_c2
t_AD
t_AD
Row
t_RASD1
Column
T_c1
T_c2
Column
t_RDD
t_CASD2
t_CASD3
t_RSD
t_RASD2
t_CASD3
t_RAC2^*3
t_ACC2^{*2 tCAC2*}t_R1DS t_RDH^*4
t_DACD1
t_DACD2 t_DACD1
t_RDH^*5
t_DACD2
t_WSD1
t_WSD2
t_WSD1
t_WSD2
t_WDD1
t_WPDD1
t_WDH t_WDD1
t_WPDH t_WPDD1
t_WDH
t_WPDH
t_DACD3
t_DACD3
t_DACD3 t_DACD3
Notes: 1. For t_CAC2, use t_cyc × (n + 1) – 25 instead of t_cyc × (n + 1) – t_CASD2 – t_RDS.
2. For t_ACC2, use t_cyc × (n + 2) – 30 instead of t_cyc × (n + 2) – t_AD – t_RDS.
3. For t_RAC2, use t_cyc × (n + 2.5) – 20 instead of t_cyc × (n + 2.5) – t_RASD2 – t_RDS.
4. t_RDH is measured from A21–A0 or CAS, whichever is negated first.
5. t_RDH is measured from A21–A0, RAS, or CAS whichever is negated first.
Figure 20.14 DRAM Bus Cycle: (Long-Pitch, High-Speed Page Mode)
Rev. 7.00 Jan 31, 2006 page 492 of 658
REJ09B0272-0700