SH7032 Datasheet, PDF (526/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 Electrical Characteristics
Item
Symbol Min Max
Unit Figures
DACK0, DACK1 delay time 1 t_DACD1 — 40
DACK0, DACK1 delay time 2 t_DACD2 — 40
DACK0, DACK1 delay time 3*⁵ t_DACD3 — 40
ns 20.21, 20.22, 20.24–
ns ^{20.27, 20.32, 20.33}
ns 20.22, 20.26, 20.27,
20.32
DACK0, DACK1 delay time 4 t_DACD4 — 40
ns 20.24, 20.25
DACK0, DACK1 delay time 5 t_DACD5 — 40
ns
Read delay time 35% duty*¹ t_RDD
— t_cyc × 0.35 + 35
ns
20.21, 20.22, 20.24-
50% duty
— t_cyc × 0.5 + 35
ns ^{20.28, 20.32}
Data setup time for CAS
t_DS
0*³ —
ns 20.24, 20.26
CAS setup time for RAS
t_CSR
10 —
ns 20.29–20.31
Row address hold time
t_RAH
10 —
ns 20.24, 20.26
Write command hold time
Write command 35% duty*¹
setup time
50% duty
t_WCH
t_WCS
t_WCS
15 —
0—
0—
ns
ns 20.24
ns
Access time from CAS
precharge*⁴
t_ACP
tcyc —
–20
ns 20.25
Notes: 1. When frequency is 10 MHz or more.
2. n is the number of wait cycles.
3. –5 ns for parity output of DRAM long-pitch access
4. It is not necessary to meet the t_RDS specification as long as the access time
specification is met.
5. In the relationship of t_CASD2 and t_CASD3 with respect to t_DACD3, a Min-Max combination
does not occur because of the logic structure.
Rev. 7.00 Jan 31, 2006 page 500 of 658
REJ09B0272-0700