SH7032 Datasheet, PDF (306/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
GR Setting in Complementary PWM Mode: Note the following when setting the general
registers in complementary PWM mode and when making changes during operation.
• Initial values: Settings from H'0000 to T–1 (T: TCNT3 initial setting) are prohibited. After
counting starts, this setting is allowed from the point when the first A3 compare match occurs.
• Methods of changing settings: Use buffer operation. Writing directly to general registers may
result in incorrect waveform output.
• When changing settings: See figure 10.38.
GRA3
GR
H' 0000
BR
Prohibited
GR
Figure 10.38 Example of Changing GR Settings with Buffer Operation (1)
Buffer Transfers when Changing from Increment to Decrement: When the contents of GR are
in the range GRA3 – T + 1 to GRA3, do not transfer a value outside this range. When the contents
of GR are outside this range, do not a transfer a value within it. Figure 10.39 illustrates a point for
caution regarding changing of GR settings with buffer operation.
GRA3 + 1
GRA3
GRA3 – T + 1
GRA3 – T
Changes prohibited
TCNT3
TCNT4
Figure 10.39 Caution on Changing GR Settings with Buffer Operation (1)
Buffer Transfers when Changing from Decrement to Increment: When the contents of GR are
in the range H'0000 to T–1, do not transfer a value outside this range. When the contents of GR
are outside this range, do not transfer a value within it. Figure 10.40 illustrates this point for
caution regarding changing of GR settings with buffer operation
Rev. 7.00 Jan 31, 2006 page 280 of 658
REJ09B0272-0700