SH7032 Datasheet, PDF (331/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6.15 ITU Operating Modes
Table 10.18 ITU Operating Modes (Channel 0)
Register Setting
TSNC
TMDR
TFCR
TOCR
TIOR0
TCR0
Reset
Output
Operating
Comp Sync
Level
Mode
Sync MDF FDIR PWM PWM PWM Buffer Select IOA
IOB
Clear Clock
Select Select
Synch- SYNC0 — — √
———
—
√
√
ronized = 1
preset
√
√
PWM
√
— — PWM0 — — —
—
—
√*
=1
√
√
Output √
compare A
function
— — PWM0 — — —
—
IOA2 = 0, √
=0
others:
don’t care
√
√
Output √
compare B
function
—— √
———
—
√
IOB2 = 0, √
√
others:
don’t care
Input
√
capture A
function
— — PWM0 — — —
—
IOA2 = 1, √
=0
others:
don’t care
√
√
Input
√
capture B
function
— — PWM0 — — —
—
√
=0
IOB2 = 1, √
√
others:
don’t care
Counter Clear Function
Clear at √
—— √
———
—
√
√
compare
match/
input
capture A
CCLR1 √
=0
CCLR0
=1
Clear at √
—— √
———
—
√
√
compare
match/
input
capture B
CCLR1 √
=1
CCLR0
=0
Synch- SYNC0 — — √
———
—
√
√
ronized = 1
clear
CCLR1 √
=1
CCLR0
=1
√: Settable, —: Setting does not affect current mode
Note: * In PWM mode, the input capture function cannot be used. When compare match A and
compare match B occur simultaneously, the compare match signal is inhibited.
Rev. 7.00 Jan 31, 2006 page 305 of 658
REJ09B0272-0700