SH7032 Datasheet, PDF (594/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Bit Name
Address Register 7
6
5
4
3
2
1
0
Module
H'5FFFFD2– —
H'5FFFFED
—
—
—
—
—
— — — PFC
H'5FFFFEE CASCR CASH CASH CASL CASL —
MD1 MD0 MD1 MD0
———
H'5FFFFEF
—
—
—
—
—
— — — TPC
H'5FFFFF0 TPMR —
—
—
—
G3N G2N G1N G0N
OV OV OV OV
H'5FFFFF1 TPCR
G3C G3C
MS1 MS0
G2C
MS1
G2C G1C G1C G0C G0C
MS0 MS1 MS0 MS1 MS0
H'5FFFFF2 NDERB NDE NDE
R15 R14
NDE
R13
NDE NDE NDE NDE NDE
R12 R11 R10 R9 R8
H'5FFFFF3 NDERA
H'5FFFFF4
H'5FFFFF5
H'5FFFFF6
NDRB*⁴
NDRA*⁴
NDRB*⁴
H'5FFFFF7 NDRA*⁴
NDE NDE
R7
R6
NDE
R5
NDE NDE NDE NDE NDE
R4 R3 R2 R1 R0
NDR15 NDR14 NDR13 NDR12 —
———
NDR7 NDR6 NDR5 NDR4 —
———
—
—
—
—
NDR11 NDR1 NDR9 NDR8
0
—
—
—
—
NDR3 NDR2 NDR1 NDR0
H'5FFFFF8– —
—
—
—
—
—
———
H'5FFFFFF
Notes
1. Only 8-bit accessible. 16-bit and 32-bit access disabled.
2. Register shared by all channels.
3. Address for read. For writing, the addresses are H'5FFFFB8 for TCR and TCNT and
H'5FFFFBA for RSTCSR. For more information, see section 12, Watchdog Timer
(WDT), particularly section 12.2.4, Notes on Register Access.
4. When the output triggers for TPC output group 0 and TPC output group 1 set by TPCR
are the same, the NDRA address is H'5FFFFF5; when the output triggers are different,
the NDRA address for group 0 is H'5FFFFF7 and the NDRA address for group 1 is
H'5FFFFF5. Likewise, when the output triggers for TPC output group 2 and TPC output
group 3 set by TPCR are the same, the NDRB address is H'5FFFFF4; when the output
triggers are different, the NDRB address for group 2 is H'5FFFFF6 and the NDRB
address for group 3 is H'5FFFFF4.
5. 16-bit and 32-bit accessible. 8-bit access disabled.
Rev. 7.00 Jan 31, 2006 page 568 of 658
REJ09B0272-0700